While the active part of electrolytic capacitors, the so-called wound cell, consists of aluminum anode and cathode foil , paper, and electrolyte, the film capacitor is made of metal-coated plastic film that builds its electrodes. The film capacitor is made from dry materials: the capacitor plates consist of metal vapor, which was been deposited on a plastic film that serves as dielectric.
Often, the dielectric is polypropylene, consisting of polymer chains that are preferably oriented in longitudinal and horizontal direction also known as BOPP for biaxially oriented polypropylene. The different electrical properties of the two technologies originate from the different materials used in them. Figure 3 shows the energy densities for some selected dielectrics in comparison. Actual aluminum electrolytic capacitors have up to ten times higher energy density than polypropylene film capacitors.
Because the electrical current flow in aluminum electrolytic capacitors is facilitated by ions flowing through the electrolyte, the viscosity of the electrolyte has a significant influence on the temperature dependence of the ESR values: at low temperatures the electrolyte becomes more viscous and inhibits the free movement of ions, leading to a higher ESR value. Also the capacitance of aluminum electrolytic capacitors decreases with falling temperatures by a double-digit percentage.
These parameters show a similar performance vs. The film capacitor offers higher rated voltages than the e-cap: the voltage proof of a single element can be up to V, while e-cap rated voltages are limited to V [3]. When connecting electrolytic capacitors in series, an active or passive balancing is beneficial to ensure a uniform distribution of the DC-link circuit voltage on the individual capacitor.
Comparison of aging, failure modes and important stressors of electrolytic capacitors vs. Defects in the film capacitor, however, are burnt and thus electrically isolated, but each burnt defect causes a small loss of dielectric film, i. The operating parameters temperature, voltage, and ripple current determine the lifetime of electrolytic capacitors.
For film capacitors, temperature, voltage, and humidity limit the lifetime. The cost is an important criterion in the choice of a technology: the specific cost to store a given amount of energy with aluminum electrolytic capacitors is significantly less approximately by a factor of three than with film capacitors.
These significant differences suggest that both technologies will stay available on the market in the future. Summary Modern power electronics designs require compact DC link circuit capacitors with long life spans. Aluminum electrolytic capacitors convince with high specific energy densities and foil capacitors offer great ripple current capability.
Both technologies have physical limits based on their design and the materials used. A capacitor stack etch mask is formed over the aluminum oxide hardmask layer, and portions of the aluminum oxide layer and the optional titanium aluminum nitride layer are etched using reactive ion etching RIE to form the hardmask. The exposed capacitor layers e. Thereafter, a hydrogen diffusion barrier structure is formed over the ferroelectric capacitor, a dielectric material is formed over the barrier structure, and a second contact is formed through the dielectric material for connection of the upper capacitor electrode in subsequent metalization layers or levels.
The following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed. The present invention will now be described with reference to the attached drawing figures, wherein like reference numerals are used to refer to like elements throughout. The invention relates to semiconductor device fabrication and the use of aluminum oxide hardmasks for patterning ferroelectric capacitor stack structures.
The invention may be carried out in any type of semiconductor device, for example, devices having memory cells with ferroelectric cell capacitors or other devices in which ferroelectric capacitors are used. The various aspects and advantages of the invention are hereinafter illustrated and described in conjunction with the drawings, wherein the illustrated structures are not necessarily drawn to scale.
Referring initially to FIGS. As shown in FIG. A sidewall diffusion barrier 46 is formed over the capacitor C, including an aluminum oxide AlO X material and a silicon nitride material SiN. A first inter-level or inter-layer dielectric ILD 0 24 is formed over the barrier 46 , and conductive contacts 26 are formed through the dielectric 24 and through the barrier 46 to couple with the upper capacitor electrode 22 plateline and with the bitline contact 16 in the PMD level In FIG.
An initial or lower titanium aluminum nitride TiAlN layer 30 is deposited over the PMD 14 and over the contact 16 , and a bi-layer lower electrode 18 is formed over the TiAlN 30 , including an iridium layer Ir 18 a and an iridium oxide layer IrO 18 b. A PZT ferroelectric layer 20 is deposited over the lower electrode layer 18 b and an upper bi-layer electrode 22 is formed over the ferroelectric 20 , including an iridium oxide layer IrO 22 a and an iridium layer Ir 22 b.
In the device 2 , three hardmask layers 32 , 34 , and 36 are then deposited over the upper electrode 22 , including another TiAlN layer 32 , a titanium aluminum oxynitride TiAlON layer 34 , and an uppermost TiAlN layer A hardmask etch 42 is performed in FIG. As discussed above, the ferroelectric capacitor C and the ferroelectric material 20 thereof are degraded by exposure to hydrogen during fabrication processing.
The inventors have appreciated that ferroelectric films may be severely degraded by exposure to hydrogen in back-end processing found in many CMOS integration schemes. These cracks 48 leave hydrogen diffusion channels through which process related hydrogen can migrate into the capacitor stack C and degrade or impair device performance e.
Thus, although the bi-layer diffusion barrier 46 may operate to inhibit lateral diffusion into the PZT material 20 , the upper portion of the stack is subject to hydrogen ingress during subsequent processing.
The tri-layer hardmask 32 - 36 is further problematic in fabrication, due to difficulties in adjusting deposition conditions to transition between formation of TiAlN 32 to TiAlON 34 and back to TiAlN 36 , while trying to control the amount of oxygen content in the TiAlON 34 to avoid high resistivity. With respect to preventing or inhibiting hydrogen degradation, cracks that occur at or before etching openings through the ILD 0 material 24 e. In the example device 2 , the bi-layer structure 46 is theoretically intended to prevent hydrogen damage.
In particular, the deposition of the AlOx layer is generally a hydrogen-free process, but the subsequent deposition of the SiN layer is a hydrogenating process. The SiN is used because this material operates both as a hydrogen diffusion barrier and also as an etch-stop layer in performing the VIA 0 etch through the ILD 0 material The AlO X layer inhibits hydrogen ingress, while being generally non-reactive with respect to the ferroelectric material.
Cracks 48 also extend into and through the barrier AlO X , because it is relatively thin, resulting in a diffusion path for hydrogen. The cracks 48 are believed to originate at grain boundaries, and depending on the stress changes that the patterned capacitor goes through during processing, the grain boundaries act as crack propagation sites. The formation of the SiN layer is believed to start these fractures as the SiN is a highly compressive film, whereas the AlO X and the other stack layers are generally tensile films.
As illustrated and described further below, the invention provides capacitor stack etch hardmasks allowing integration of ferroelectric cell capacitor fabrication in conjunction with existing back-end interconnect e. Referring now to FIGS.
While the method is illustrated in FIG. In addition, not all illustrated steps may be required to implement a methodology in accordance with the present invention. The methods according to the present invention, moreover, may be implemented in association with the fabrication of devices illustrated and described herein as well as in association with other devices and structures not illustrated.
For example, the exemplary method may be employed in fabricating a semiconductor device as illustrated and described below with respect to FIGS. Also, SrTa 2 O 6 materials may be employed in hardmasks used to form capacitors using PZT or other ferroelectric materials, wherein all such variant implementations are contemplated as falling within the scope of the present invention. In addition, while the exemplary semiconductor devices are illustrated herein with ferroelectric capacitors formed in a dielectric layer or level after front-end contact formation and prior to formation of overlying metalization levels, the invention may be employed at other points in a fabrication process, for example, wherein the ferroelectric capacitors are formed at any level in a multi-level semiconductor device design.
Furthermore, the invention may be employed in semiconductor devices fabricated on or in any type of semiconductor body, including but not limited to silicon substrates, SOI wafers, epitaxial layers formed above a substrate, etc.
In this regard, the invention is not limited to the examples illustrated and described herein, and all variant implementations providing aluminum oxide hardmasks are contemplated as falling within the scope of the present invention and the appended claims.
Beginning at in FIG. At , transistors are formed for logic or analog circuitry and for ferroelectric memory cells, and an initial dielectric material is formed over the transistors, referred to herein as a poly-metal dielectric PMD. Conductive contacts e.
Any suitable front-end and transistor fabrication processing techniques and materials may be employed at and within the scope of the invention. At , ferroelectric capacitor layers are formed over the PMD and contacts, including formation of upper and lower conductive capacitor electrode layers and a ferroelectric material layer between the electrode layers.
Any suitable materials, material thicknesses, and layer formation processes may be employed in forming the ferroelectric capacitor material layers at within the scope of the invention. For example, in the device illustrated and described below with respect to FIGS. In the illustrated device below, the upper electrode is a bi-layer comprising an IrO layer formed over the PZT ferroelectric material, and an Ir layer formed over the IrO layer, wherein the electrode and ferroelectric layers may be formed at to any desired thickness in accordance with the invention.
Preferably, a first layer is comprised of iridium oxide preferably less than nm thick—more preferably less than 50 nm thick and a second layer is comprised of iridium preferably less than nm thick—more preferably less than 50 nm thick.
Film capacitor basics Film capacitors are known under a variety of different names including, plastic film capacitors, film dielectric capacitors, or polymer film capacitors, and metallised film capacitors. Polypropylene film capacitor Film capacitor construction There are two main formats for the construction of film capacitors.
Film foil: This form of film capacitor has two metal foil electrodes that are separated by the plastic film. The terminals are typically connected to the end-faces of the electrodes by means of welding or soldering.
Metallised film: In this type of film capacitor the plastic film has a very thin layer of metallisation deposited onto the film. The thin metal layer is typically only 0. This is vacuum deposited onto the plastic film. My leaving a small area free of metallisation at either end, it is possible to connect the metallisation to one connection or the other of the film capacitor.
Self healing One aspect of film capacitors is that of self-healing. Film capacitor dielectrics Many of the dielectric are known by their common names and they also have abbreviations.
These film capacitors are low cost types and relatively small for their capacitance. They are generally used for general purpose electronic applications.. Polyester film capacitor One downside of this type of film capacitor is that it can introduce noise when used in applications where there is vibration. Read more about polyester capacitors Polycarbonate, PC: Although a very successful and useful form of film capacitor, this type is no longer made because the manufacturer of the film ceased production of it around the year The nearest replacement type is generally considered to be the PP, polypropylene dielectric.
As a result they are often used in timing circuits, filters and other precision analogue applications. This type of film capacitor introduces moderate level of loss which can increase with frequency. As a result of laterally offset position of electrodes , with wall extending therebetween, the conductive material will not short the electrodes , together even when a vertical defect exists in the dielectric wall between the electrodes , Moreover, essentially vertically depositing the electrode material from source prevents shorting the electrodes if a horizontal defect exists in the dielectric layer as the conductive material is directionally deposited and will not travel far enough horizontally to completely fill a horizontal defect through the wall That is, at least a portion of any horizontal defect will remain vacant and be a space filled with air or gas depending on the processing conditions of the particular process.
Further, all of the conductive material on top of wall is removed by patterning or planarization. In the event that that a defect exists at the very top of wall , the patterning or planarization will remove the conductive material and defect. The present disclosure provides a benefit over prior capacitors in integrated circuits. In step , an interposer substrate is prepared. The interposer substrate is adapted to provide off-die electrical functionality for digit or analog signal processing dies to which the interposer substrate will connect.
In step , laterally adjacent electrodes for a capacitor are formed on a dielectric layer on the interposer substrate. In an embodiment, the laterally adjacent electrodes have a dimension adjacent each other that is less than their lateral dimension. For example, the height of the FIGS. It will be appreciated that the electrodes are formed by negative process in an embodiment. In step , the capacitor electrodes are insulated or covered by a further dielectric material.
Connections are formed to each of the electrodes, step The connections are connected to other circuitry, step Capacitor has a first electrode , and a second electrode , laterally adjacent to each other. The electrodes can be fabricated according to either the FIG. Accordingly, both pairs of electrode reference numbers , and , are used to designate the electrodes in FIG.
The electrode pairs , and , are separated by a dielectric material from either layer or depending on the fabrication process. Electrically conductive connections and are fabricated through layer Connections and respectively provide electrical communication to individual plates and or and of the capacitor. Connections and connect to further circuitry. In this embodiment, the dielectric material intermediate the electrodes , or , is elongate and extends between a plurality of plates of the capacitor.
The connections and extend to electrode plates , or , as described herein. Using an array of capacitors provides the flexibility to provide the capacitance needed for a particular application by connecting only certain groups of the connections and to provide the required capacitance. For required capacitance, the design of electrode could be flexible. In some applications, some of the electrode plates , or , would remain unconnected to external circuits and hence would not add to the capacitance.
The electrical circuit includes a wireless communication device Wireless communication device is used to link system with a further electronic system such as a telephone network, local area network, wide area network or the internet.
The wireless communication device operates according to orthogonal frequency-division multiplexing OFDM in an embodiment. For additional information regarding IEEE In an embodiment, interface includes at least one conductive bonds, traces, conductors, and electrically conductive lines. In an embodiment, interface is a power supply line. In an embodiment, interface is control signal or address line s.
An interposer having a capacitor according to the teachings herein and equivalents is connected to conductive interface In an embodiment, a first group of capacitor first electrodes are connected to interface A second group of capacitor second electrodes are connected to a node separate from interface in the electric circuit In an embodiment, the node is a grounded node. As described in the embodiments above, capacitor includes co-planar electrodes separated laterally by a dielectric.
While the electrical circuit is described as including a wireless communication device, electrical circuit may exclude the wireless communication device in favor of a stand alone processor. In a further embodiment, wireless communication device is a mobile telephone. In an embodiment, die includes an electronic device, such as a processor , a memory, a communication system , or an application specific integrated circuit.
Wireless communication device is used to link system die with a further electronic system such as a telephone network, local area network, wide area network or the internet. In an embodiment, device is a cellular telephone receiver or transceiver.
Die is coupled to a first surface of substrate by controlled collapse chip connection C 4 It will be recognized by one of skill in the art that other conventional structures may mechanically and electrically connect die to substrate Interposer is coupled to a second surface of substrate by a mechanical or electrical connection Examples of connection include surface mount or controlled collapse chip connection.
Conductive interconnects extend from the first surface to the second surface of substrate to couple the capacitor to die In an embodiment, interconnects are formed by filling a via in the substrate with a conductive material, such as metal.
In one embodiment, substrate is fabricated from a ceramic material. Alternatively, substrate is fabricated from an organic material. Preferably, substrate is thin, which permits a short coupling distance between the interposer with capacitor and die In one embodiment, substrate has a thickness of less than about 1 millimeter, which reduces the length of interconnects A short coupling distance reduces the inductance and resistance in the circuit in which the interposer is connected.
It will also be recognized that the capacitor could be coupled directly to die in an embodiment. While FIG. Such a location is shown in FIG. This type of assembly, with the interposer between the die and package substrate, will result in even shorter distances from the capacitor to the die.
In a further embodiment, the capacitor of an embodiment of the present invention is fabricated as a pre-formed unit that is then laminated to the package.
The integrated circuit die is thereafter connected to the capacitor on package. In an embodiment, the integrated circuit die is laminated directly to the capacitor. The above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description.
0コメント